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6 Dec 2024 SERC Institute of Microelectronics Patterning of 1µm Critical Dimension Through Silicon Via using Positive Tone Resist Mask by a Photolithography Stepper Arvind Sundaram, Riley Kang, Chandra Bhesetti Rao EPTC 2024: IEEE Electronics Packaging Technology Conference
6 Jun 2019 SERC Institute of High Performance Computing  Electroplating of Through Silicon Vias: A Kinetic Monte Carlo Model MingRui Lai, Ramanarayan Hariharaputran, Khoong Hong Khoo, Hongmei Jin, Shunnian Wu, Chaitanya Amol Joshi, Kodanda Ram Mangipudi, Siu Sin Quek, David T. Wu, Sridhar Narayanaswamy, Bharathi Madurai Srinivasan 2019 Electron Devices Technology and Manufacturing Conference (EDTM)
13 Dec 2018 SERC Institute of High Performance Computing  Multiscale Models for Electroplating of Through Silicon Vias K. H. Khoo, MingRui Lai, H. Ramanarayan, Hongmei Jin, S. Wu, C. A. Joshi, K. R. Mangipudi, J. J. Cheng, S. S. Quek, D. T. Wu, N. Sridhar, M. S. Bharathi 2018 International Wafer Level Packaging Conference (IWLPC)