| Publication date | Communities | Collections | Article title | Author(s) | Journal/Conference |
|---|---|---|---|---|---|
| 28 Nov 2019 | SERC | Institute of High Performance Computing | Defect-Free Electroplating of High Aspect Ratio Through Silicon Vias: Role of Size and Aspect Ratio | C. A. Joshi, H. Ramanarayan, K. H. Khoo, H. Jin, S. S. Quek, D. T. Wu, N. Sridhar, M. S. Bharathi | 2019 International Wafer Level Packaging Conference (IWLPC) |
| 13 Dec 2018 | SERC | Institute of High Performance Computing | Multiscale Models for Electroplating of Through Silicon Vias | K. H. Khoo, MingRui Lai, H. Ramanarayan, Hongmei Jin, S. Wu, C. A. Joshi, K. R. Mangipudi, J. J. Cheng, S. S. Quek, D. T. Wu, N. Sridhar, M. S. Bharathi | 2018 International Wafer Level Packaging Conference (IWLPC) |