Zhang, X., Lau, B. L., Feng, H., Tang, G., Jong, M. C., Bhattacharya, S., Rao, V. S., Chandra Rao, B. S. S., & Nhat Anh, T. V. (2026). Process Development of Two-Stacked Chips with a Backside Embedded Two-Phase Cooling Solution. In (Editor), 2026 IEEE 76th Electronic Components and Technology Conference (ECTC). https://doi.org/10.1109/ectc51846.2026.00096
Abstract:
Stacking two high-performance, high-power dissipation logic chips requires new cooling solutions to address the associated thermal challenges. The incumbent remote heat sink cooling solution is incapable of extracting heat efficiently from two stacked chips. This paper presents a novel process development for a backside embedded two-phase colling solution to address the thermal challenge for two-stacked high-power chips. The novel process development includes via-first large TSV (30 × 300 μm), frontside RDL for heater and sensor elements, and backside microchannels (8 × 8 mm) with micro pin-fins (100 μm). Testing results show that chip-1 dissipates a heat flux of 157W/cm2 and chip-2 dissipates a heat flux of 187W/cm2 at coolant flow rate 0.699 L/min.
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Funding Info:
This research / project is supported by the A*STAR - Applied Centre of Excellence in Advanced Packaging 3.0 (Grant No. I2101E0008)
Grant Reference no. : I2101E0008