Sub-0.5 μm Pitch Scaling of W2W Cu/Dielectric Hybrid Bonding

Sub-0.5 μm Pitch Scaling of W2W Cu/Dielectric Hybrid Bonding

2024 IEEE 74th Electronic Components and Technology Conference (ECTC)

10.1109/ECTC51529.2024.00390

https://doi.org/10.1109/ectc51529.2024.00390

Hemanth Kumar Cheemalamarri, Arvind Sundaram, San Sandra, Tran Van Nhat Anh, Bhesetti Chandra Rao, Chen Gim Guan, Yu Haitao, Mani Raju, Luo Ping, Lee Chaeeun, Vempati Srinivasa Rao, Navab Singh

26 June 2024

Cheemalamarri, H. K., Sundaram, A., Sandra, S., Van Nhat Anh, T., Chandra Rao, B., Guan, C. G., Haitao, Y., Raju, M., Ping, L., Chaeeun, L., Rao, V. S., & Singh, N. (2024). Sub-0.5 μm Pitch Scaling of W2W Cu/Dielectric Hybrid Bonding. 2024 IEEE 74th Electronic Components and Technology Conference (ECTC), 803–808. https://doi.org/10.1109/ectc51529.2024.00390

Hybrid bonding, a crucial technique in heterogeneous package integration, holds immense potential for advancing pitch scaling in semiconductor technologies. As three-dimensional (3D) nodes continue to progress, the exploration of novel materials and processes becomes imperative. This study focuses on the investigation of optimal dielectric combinations to maintain wafer integrity during bonding, aiming to achieve higher bond strength with alternative dielectrics limited to thicknesses of a few tens of nanometers. Moreover, the exploration and quantification of the minimum effective bonding area required for conventional oxide dielectrics are essential for successful fusion bonding. In this research, we employed a damascene process sequence to fabricate sub-0.5 μm pitch Cu/dielectric hybrid bonding at the wafer level. Various optimizations were emphasized, including test vehicle design and fabrication processes. Surface and interface analysis techniques were employed to scrutinize critical process steps such as post lithography, etching, electrochemical deposition (ECD), chemical mechanical planarization (CMP), and bonding overlay adjustments, aiming to realize sub-0.5 μm pitch wafer-level Cu/dielectric hybrid bonding. Our findings provide insights into advancing pitch scaling in heterogeneous package integration through meticulous material selection and process optimization.

Publisher Copyright

This research / project is supported by the Agency for Science, Technology and Research - Center of Excellence in Advanced Packaging 3.0
Grant Reference no. : I2101E0008

© 2024 IEEE.  Personal use of this material is permitted.  Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.

https://oar.a-star.edu.sg/communities-collections/articles/21968

2377-5726

Institute of Microelectronics