Zhang, X., Feng, H., Tang, G., Lau, B. L., Jong, M. C., Bhattacharya, S., & Rao, V. S. (2025). Development of an Embedded 2-Phase Cooling Solution for Two Stacked High-Power Chips in Future HPC HPC and AI Applications. In (Editor), 2025 IEEE 75th Electronic Components and Technology Conference (ECTC). https://doi.org/10.1109/ectc51687.2025.00082
Abstract:
There is increasing recognition that 3D IC promises tremendous performance advantage. However, thermal management technologies currently limit implementation. In this paper, we present the development of an embedded backside 2-phase cooling technology that enables the dissipation of high power in two stacked chips, aimed at future HPC and AI applications. The test vehicle was designed and fabricated. Testing results show that chip-1 can dissipate a heat flux of 157W/cm2 and chip-2 can dissipate a heat flux of 187W/cm2 at coolant flow rate 0.699 L/min. This is the first demonstration of an embedded 2-phase cooling solution for two stacked high-power chips
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Funding Info:
This research / project is supported by the A*STAR - Applied Centre of Excellence in Advanced Packaging 3.0 (Grant No. I2101E0008)
Grant Reference no. : Grant No. I2101E0008
This research / project is supported by the A*STAR - Council Strategic Fund
Grant Reference no. : C210415009