3D Stacking of Heterogeneous Chiplets on Modified FOWLP Platform with Thru-Silicon Redistribution Layer

3D Stacking of Heterogeneous Chiplets on Modified FOWLP Platform with Thru-Silicon Redistribution Layer

2023 IEEE 73rd Electronic Components and Technology Conference (ECTC)

10.1109/ECTC51909.2023.00012

http://dx.doi.org/10.1109/ectc51909.2023.00012

Chai Tai Chong, Lau Boon Long, Sharon Lim Pei Siang, David Ho Soon Wee, Rob van Kampen, Paul Castillou, Roberto Gaddi, Lance Barron, Mickael Renault, Jay Ko, Jonathan Hammond

03 August 2023

Chong, C. T., Long, L. B., Siang, S. L. P., Wee, D. H. S., van Kampen, R., Castillou, P., Gaddi, R., Barron, L., Renault, M., Ko, J., & Hammond, J. (2023, May). 3D Stacking of Heterogeneous Chiplets on Modified FOWLP Platform with Thru-Silicon Redistribution Layer. 2023 IEEE 73rd Electronic Components and Technology Conference (ECTC). https://doi.org/10.1109/ectc51909.2023.00012

A 3D stacking of CMOS on RF device chiplet is demonstrated for significant reduction of areal form factor for Front-End Module (FEM) application. The salient points of the process integration of thru-silicon redistribution layer on the backside of RF device wafer, chip-to-wafer bonding and assembly, measurement of the interconnection and reliability assessment will be discussed.

Publisher Copyright

There was no specific funding for the research done

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https://oar.a-star.edu.sg/communities-collections/articles/20255

2377-5726

Institute of Microelectronics