Chong, S. C., Xie, L., Sekhar, V. N., Kumar, M. D., Rao, B. S. S. C., & Rao, V. S. (2025). Process Development, Challenges, and Strategies for Void-Free Multi-Chip Stacking in Hybrid Bonding Applications. In (Editor), 2025 IEEE 75th Electronic Components and Technology Conference (ECTC). https://doi.org/10.1109/ectc51687.2025.00332
Abstract:
Multi-Chip Stacking in Hybrid bonding approach
involved the use of 50μm thin chip with double side hybrid
bonding pads. Thin chip handling is very challenging in assembly
process such as dicing, picking up the chip from dicing tape and
bond on the target substrate or wafer due to weak die strength. In
addition, hybrid bonding adds further challenges due to stringent
requirements of hybrid bonding process such as cleanliness,
particles free surface and low chip’s warpage. Hybrid bonding
voids at the bonding interface can be attributed to the entrapped
particles or residue or trapped air. In this work, we explored the
use of a soft curvature tool coupled with optimized bonding
parameters to achieve void-less bonding in multi-chip stacking.
License type:
Publisher Copyright
Funding Info:
This research / project is supported by the Agency for Science, Technology, and Research - Centre of Excellence in Advanced Packaging 3.0
Grant Reference no. : I2101E0008