Cheemalamarri, H. K., Rao, B. S. S. C., Sundaram, A., Jacky, H. S. J., Fong, T. S., Pitchappa, P., Nair, N. M., Singh, N., & Rao, V. S. (2024). Fabrication of c-Si Pillars on Glass Substrates for Terahertz Dielectric Metasurfaces Using Glass-Silicon Direct Bonding. 2024 IEEE 26th Electronics Packaging Technology Conference (EPTC), 255–259. https://doi.org/10.1109/eptc62800.2024.10909897
Abstract:
This study employs a low thermal budget glass-to-silicon direct bonding process without interlayers to fabricate 200μm thick crystalline silicon (c-Si) pillars processed on 300mm glass substrates. The process demonstrated robust bonding integrity, with no chip-off even after rigorous backgrinding procedures. Comprehensive investigations were conducted on the selection of glass substrates, the impact of cleaning processes on the bonding interface, and the optimization of these cleaning protocols. Additionally, lithography and etching processes were optimized on blank silicon wafers prior to their application on glass-bonded wafers. Challenges associated with handling glass on electrostatic chucks (ESC) were also addressed. Following these optimizations, a detailed process flow was developed for fabricating thick silicon pillars with aspect ratio ranging of 1:2. Surface and interface analyses were performed using confocal scanning acoustic microscopy, optical/laser profilometry, and X-SEM inspections. This fabrication flow shows significant potential in the fields of advanced packaging, optoelectronics, microfluidics, MEMS, and terahertz (THz) technologies.
License type:
Publisher Copyright
Funding Info:
This research / project is supported by the Agency for Science, Technology and Research - Manufacturing, Trade, and Connectivity Programmatic Fund - Terahertz Reconfigurable Intelligent Metasurfaces (TRIM) for 6G communications
Grant Reference no. : M22L1b0110