Patra, C. K., Bhattacharya, A., Das, P. K., Zhang, X., Bhattacharya, S., & Rao, V. S. (2025). Numerical Investigation of Embedded Micro Pin-Fin Two-Phase Liquid Cooling for Dual-Chip Stacks in HPC and AI Systems. In (Editor), 2025 IEEE 27th Electronics Packaging Technology Conference (EPTC). https://doi.org/10.1109/eptc67330.2025.11392657
Abstract:
The miniaturisation of semiconductor devices has driven the industry to explore 3D ICs to achieve significant performance improvements over 2D ICs. However, stacking high-performance logic chips with a limited thermal path dissipates considerable heat, making 3D IC cooling challenging. The present study establishes a 3D CFD-heat transfer model to test the efficacy of the embedded two-phase cooling technique to address the thermal management challenges in a two-stacked logic chips. The developed model is validated against existing literature. Afterwards, the model is used for carrying out parametric studies with varying flow rate in the range of 140 ml/min - 490 ml/min and chip size from 10 × 10 mm2 - 30 × 30 mm2. For two-stacked chips with dimensions of 10 × 10 mm2, a maximum dissipated heat flux of 768.6 W/cm2 is achieved for a flow rate of 490 ml/min. A dissipated power of 1693.9 W is achieved for two-stacked chips with dimensions of 30 × 30 mm² at a fixed flow rate of 140 ml/min, with a pumping power of 0.63 W.
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Publisher Copyright
Funding Info:
This research / project is supported by the A*STAR - IME-Applied Centre of Excellence in Advanced Packaging 3.0 (Grant No. I2101E0008).
Grant Reference no. : I2101E0008