Identify critical packaging parameters impacting wafer warpage using FEA and statistical analysis techniques

Identify critical packaging parameters impacting wafer warpage using FEA and statistical analysis techniques

2023 IEEE 25th Electronics Packaging Technology Conference (EPTC)

10.1109/EPTC59621.2023.10457923

http://dx.doi.org/10.1109/eptc59621.2023.10457923

Ji Lin, Ng Yong Chyn

18 March 2024

Lin, J., & Chyn, N. Y. (2023, December 5). Identify critical packaging parameters impacting wafer warpage using FEA and statistical analysis techniques. 2023 IEEE 25th Electronics Packaging Technology Conference (EPTC). https://doi.org/10.1109/eptc59621.2023.10457923

Wafer warpage behaviors that result from thermal expansion coefficient (CTE) mismatch during packaging processes are usually complicated due to the interactive influences from materials, package designs and heating histories etc. Poorly controlled wafer warpage would affect the process precision adversely and even interrupt the process when exceeding the equipment's wafer handling limit. The optimization on the material selections, design parameters, and process conditions hence becomes critical to the wafer warpage control. Parametric studies using Finite Element Analysis (FEA) simulations are often performed prior to the actual wafer processes to examine the critical factors so that the warpage could be controlled accordingly. However, such conventional parametric study approach may oversimplify the complex system as it relies on predefined parameters. Therefore, this paper describes a hybrid approach combining FEA simulations with statistical analysis for a more efficient way to quantify the influence of each parameter on wafer warpage during complex heterogeneous integration processes. This approach allows all the relevant parameters (material, design and process variables, and their interactions) of the wafer processes to be evaluated simultaneously and systematically. By performing the regression analysis, the wafer warpage prediction formula is derived. Hence the potential high wafer warpage could be mitigated as early as in the design stage by screening the variables of interest and performing associated optimizations via such warpage prediction equations.

Publisher Copyright

This research / project is supported by the National Research Foundation, Singapore - Through-SiC-Interposer Fabrication and Heterogeneous Integration Development (SHINE project)
Grant Reference no. : NA

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