High Density Redistribution Layers (< 2 µm L/S) for Chiplets Packaging

High Density Redistribution Layers (< 2 µm L/S) for Chiplets Packaging

2021 IEEE 23rd Electronics Packaging Technology Conference (EPTC)

10.1109/EPTC53413.2021.9663962

http://dx.doi.org/10.1109/eptc53413.2021.9663962

Soon Wee Ho, Chockanathan Vinoth Kanna, Jong Ming Chinq, Chai Tai Chong

05 January 2022

Ho, S. W., Kanna, C. V., Chinq, J. M., & Chong, C. T. (2021). High Density Redistribution Layers (< 2 µm L/S) for Chiplets Packaging. 2021 IEEE 23rd Electronics Packaging Technology Conference (EPTC). https://doi.org/10.1109/eptc53413.2021.9663962

Increased demand for chiplets-based designs in advanced packages for leading applications like artificial intelligence and high power computing is driving the need for finer Cu distribution layers to meet their package I/O density and bandwidth performance requirements. In this paper, we demonstrate the feasibility of SAP method for 0.8 and 1μm Cu redistribution lines on multi-layer RDL. Electrical test results on meander comb lines and daisy chains structure show good connectivity for fine-pitch and high-density Cu RDL for chiplets packaging.

Publisher Copyright

This research / project is supported by the A*STAR - IPP-IAF - Fan-Out Wafer-Level-Packaging (FO-WLP) Development Line
Grant Reference no. : 1528100051

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https://oar.a-star.edu.sg/communities-collections/articles/18747

978-1-6654-1619-1

Institute of Microelectronics