CMOS-Compatible 200 mm 0.25 µm GaN-on-Si HEMT Process for FR3 Application

CMOS-Compatible 200 mm 0.25 µm GaN-on-Si HEMT Process for FR3 Application

2026 10th IEEE Electron Devices Technology and Manufacturing Conference (EDTM)

10.1109/EDTM65772.2026.11497271

https://doi.org/10.1109/edtm65772.2026.11497271

Qingyun Xie, Yuan Gao, Hsien-Shun Wu, Yi Heng Leong, Hanlin Xie, Haorui Luo, Hui Teng Tan, Zhan Jiang Quek, Wee Leng Ong, Lakshmi Kanta Bera, Navab Singh, Geok Ing Ng

06 May 2026

Xie, Q., Gao, Y., Wu, H.-S., Leong, Y. H., Xie, H., Luo, H., Tan, H. T., Jiang Quek, Z., Ong, W. L., Kanta Bera, L., Singh, N., & Ng, G. I. (2026). CMOS-Compatible 200 mm 0.25 µm GaN-on-Si HEMT Process for FR3 Application. In (Editor), 2026 10th IEEE Electron Devices Technology Manufacturing Conference (EDTM). https://doi.org/10.1109/edtm65772.2026.11497271

This paper reports a CMOS-compatible 200 mm 0.25 µm GaN-on-Si high electron mobility transistor (HEMT) process suitable for FR3 application. Competitive RF power performance was achieved across a range of VDS,Q, including maximum output power (Psat) of 2.3 W/mm, and a peak power-added efficiency (PAE) of 53%. The results were achieved by a GaN-on-Si process which uses commercially sourced epitaxial wafers, Al-based interconnects, and a subtractive process, making the reported process friendly for transfer to CMOS foundries.

Publisher Copyright

This research / project is supported by the A*STAR - White Space Manufacturing, Trade, and Connectivity Funding
Grant Reference no. : M23WSNG001

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https://oar.a-star.edu.sg/communities-collections/articles/23198

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Institute of Microelectronics