Vertical Interconnects Characterization for 448 Gbps/lane Co-Packaged Optics using Double-Sided Probing Method

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Vertical Interconnects Characterization for 448 Gbps/lane Co-Packaged Optics using Double-Sided Probing Method
Title:
Vertical Interconnects Characterization for 448 Gbps/lane Co-Packaged Optics using Double-Sided Probing Method
Journal Title:
2026 IEEE 76th Electronic Components and Technology Conference (ECTC)
Keywords:
Publication Date:
17 June 2026
Citation:
Wu, J., Gourikutty, S. B. N., Lim, T. G., & Bhattacharya, S. (2026). Vertical Interconnects Characterization for 448 Gbps/lane Co-Packaged Optics using Double-Sided Probing Method. In (Editor), 2026 IEEE 76th Electronic Components and Technology Conference (ECTC). https://doi.org/10.1109/ectc51846.2026.00144
Abstract:
Co-Packaged Optics (CPO) shortens the electrical distance between optical engines (OEs) and switch ASICs to overcome electrical I/O bottlenecks for next-generation AI systems, driving the need for 448 Gb/s/lane PAM4 electrical interconnects with bandwidth approaching 110 GHz. This work characterizes and compares four vertical interconnect technologies for OE I/O routing: a substrate-based via (SUB-VIA), Through-Mold Via (TMV), Through-Silicon Via (TSV), and Through-Glass Via (TGV). RF performance is measured using a direct double-sided probing method to obtain S-parameters, avoiding the accuracy and bandwidth limitations of conventional back-to-back de-embedding. Single-ended GSG TSV and TGV are measured up to 110 GHz, while GSG SUB-VIA and GSSG differential TMV transition are measured up to 65 GHz and 50 GHz, respectively. 3D full-wave EM models are developed and show good agreement with measurements over the respective frequency bands. Based on the measurement-calibrated simulation models, GSSG differential OE I/O transitions from EIC to package substrate are designed and simulated. All transitions maintain >10 dB return loss from DC to 120 GHz, with simulated insertion loss at 112 GHz of 0.60 dB (SUB-VIA), 0.87 dB (TMV), 0.37 dB (TSV), and 0.13 dB (TGV). Time-domain simulations at 448 Gb/s PAM4 show clear eye openings without Tx/Rx amplification/equalization, with TGV and TSV achieving the best margins. These results identify TGV as a strong candidate for future high-density 448 Gb/s/lane CPO electrical I/O routing.
License type:
Publisher Copyright
Funding Info:
This research / project is supported by the A*STAR - IME-Applied Centre of Excellence in Advanced Packaging 3.0 (Packaging 3.0)
Grant Reference no. : H21-MCP0080 / (old) I2101E0008
Description:
© 2026 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
ISSN:
9798331564179
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