Wang, B., Wong, M. M., Li, D., Chong, Y. S., Zhou, J., Wong, W. F., Peh, L., Mani, A., Upadhyay, M., Balaji, A., & Do, A. T. (2023, May 21). 1.7pJ/SOP Neuromorphic Processor with Integrated Partial Sum Routers for In-Network Computing. 2023 IEEE International Symposium on Circuits and Systems (ISCAS). https://doi.org/10.1109/iscas46773.2023.10181759
Abstract:
Conventional neuromorphic accelerators primarily leverage split-merge method to accommodate a neural network that is beyond a single core's size, leading to possible accuracy loss, extra core usage and significant power and energy overhead. This work presents an energy-efficient, reconfigurable neuro-morphic processor to address the problem by (i) a partial sum router circuitry that enables in-network computing to remove the need of extra merge cores; (ii) software-defined Networks-on-Chip that eliminates the power-hungry routing compute and (iii) fine-grained power gating and clock gating technique for power reduction. Our test chip achieves lossless mapping as the algorithm and an energy efficiency of 1.7pJ/SOP at 0.5V, 19% lower than state-of-the-art result.
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Funding Info:
This research / project is supported by the National Research Foundation - Competitive Research Programme
Grant Reference no. : NRF-CRP23- 2019-0003
This research / project is supported by the Singapore University of Technology and Design (SUTD) - MOE AcRF Tier-1 Grant via SUTD Start-Up Research Grant
Grant Reference no. : SRT3IS20162
This research / project is supported by the Singapore University of Technology and Design (SUTD) - MOE AcRF Tier-1 Grant via SUTD Growth Plan Grant – AI Sector
Grant Reference no. : SGP-AIRS1841
This research / project is supported by the Singapore University of Technology and Design (SUTD) - MOE AcRF Tier-1 Grant via SUTD-ZJU IDEA Visiting Professors Grant
Grant Reference no. : SUTD-ZJU(VP)201808