Y. Liu et al., "Low-Latency Hardware Accelerator for Real-Time Neural Network-Based Qubit-State Discrimination," APS Global Physics Summit 2025, Anaheim, California, United States, 2025.
Abstract:
Fast, high-fidelity processing of qubit readout signals is essential for advancing quantum processors, particularly in supporting effective quantum error correction. While neural networks (NNs) have demonstrated significant potential in achieving high-fidelity qubit-state discrimination, their computational demands can lead to substantial processing latency. This work presents a hardware accelerator designed for low-latency implementation of an optimized fully connected neural network (FCNN) for real-time multi-qubit-state discrimination. Inspired by [1], our FCNN incorporates quantization-aware training and features a streamlined 4-layer architecture. This results in a 51.3x reduction in parameters, down to 31,879, with only a 0.3% decrease in discrimination accuracy, achieving a final accuracy of 90.86%. The hardware accelerator utilizes a scalable array of multipliers and adders for parallel processing, effectively minimizing latency while maintaining a compact silicon footprint. It is suitable for implementation on both FPGAs and ASICs.
License type:
Publisher Copyright
Funding Info:
This research / project is supported by the A*STAR - NA
Grant Reference no. : C210917009
This research / project is supported by the National Research Foundation, Singapore - Quantum Engineering Programme 2.0
Grant Reference no. : NR2021-QEP2-03-P07