Zang, Q., Goh, W. L., Chong, Y. S., Do, A. T. (2023, June 11). 4b/4b/8b Precision Charge-Domain 8T-SRAM Based CiM for CNN Processing. 2023 IEEE 5th International Conference on Artificial Intelligence Circuits and Systems (AICAS). https://doi.org/10.1109/aicas57966.2023.10168593
Abstract:
Compute-in-memory (CiM) is a promising solution for solving the bottleneck of frequent data movement between the memory and processor in Von-Neumann architecture. In conventional multi-bit CiM architecture, when computing N-bit input and N-bit weight MAC operation, 2 N 1 cycles are needed for N-bit input modulation and normally 3-4−cycles with complex switch operation are needed for N-bit weight realization, which significantly degrades the final throughput and power efficiency. In this work, a C-2C DAC built in the 8T SRAM CiM array is designed for 4-bit weight and 4-bit input MAC operation, which can be completed in just one cycle. In the final power efficiency evaluation, our 4b/4b/8b CiM architecture attained up to 640 TOPS/W (normalized to 1b/1b/1b precision) which is a 6-10 times improvement as compared to the conventional multi-bit CiM architectures. The proposed architecture with 4b/4b/8b precision can provide 91.47% and 68.10% accuracy on CIFAR-10 and CIFAR-100 dataset classification, respectively.
License type:
Publisher Copyright
Funding Info:
This research / project is supported by the A*STAR - Spin-Orbit Technologies for intelligence at the Edge (SpOT-LITE)
Grant Reference no. : A18A6b0057