| Publication date | Communities | Collections | Article title | Author(s) | Journal/Conference |
|---|---|---|---|---|---|
| 10 Aug 2021 | SERC | Institute of Microelectronics | Design and Development of High Density Fan-Out Wafer Level Package (HD-FOWLP) for Deep Neural Network (DNN) Chiplet Accelerators using Advanced Interface Bus (AIB) | Mihai D. Rotaru, Wei Tang, Dutta Rahul, Zhengya Zhang | 2021 IEEE 71st Electronic Components and Technology Conference (ECTC) |