Publication date | Communities | Collections | Article title | Author(s) | Journal/Conference |
---|---|---|---|---|---|
8 Oct 2014 | SERC | Institute of Microelectronics | BIST Methodology, Architecture and Circuits for Pre-Bond TSV Testing in 3D Stacking IC Systems | Minkyu Je, Xin Liu, Philippe Royannez, Jun Zhou, Roshan Weerasekera, Bin Zhao, Chao Wang | IEEE Transactions on Circuits and Systems I: Regular Papers |