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5 Jan 2022
SERC
Institute of Microelectronics
Wafer-to-Wafer Hybrid Bonding Challenges for 3D IC Applications
H. Y. Li,
Hong Miao Ji,
Alfred Neo Siang Kiat,
Masaya Kawano
2021 IEEE 23rd Electronics Packaging Technology Conference (EPTC)
5 Jan 2022
SERC
Institute of Microelectronics
Thermal Effect Investigation of Chip-to-Wafer Hybrid Bonding on 3D-Stacked Memory
Yong Han,
Masaya Kawano
2021 IEEE 23rd Electronics Packaging Technology Conference (EPTC)
5 Jan 2022
SERC
Institute of Microelectronics
Silicon Isolation Trench Integration for the 4-stack Memory Wafer
Xiangyu Wang,
Masaya Kawano,
B.S.S. Chandra Rao
2021 IEEE 23rd Electronics Packaging Technology Conference (EPTC)
5 Jan 2022
SERC
Institute of Microelectronics
Numerical study on wafer level warpage evolution during chip to wafer hybrid bonding process
Lin Ji,
Masaya Kawano,
Sasi Kumar Tippabhotla,
Woon Leng Loh
2021 IEEE 23rd Electronics Packaging Technology Conference (EPTC)
10 Aug 2021
SERC
Institute of Microelectronics
One-step TSV process development for 4-layer wafer stacked DRAM
Masaya Kawano,
Xiang-Yu Wang,
Qin Ren,
Woon-Leng Loh,
BSS. Chandra Rao,
King-Jien Chui
2021 IEEE 71st Electronic Components and Technology Conference (ECTC)
10 Aug 2021
SERC
Institute of Microelectronics
Dielectric Materials Characterization for Hybrid Bonding
Vivek Chidambaram,
Prayudi Lianto,
Xiangyu Wang,
Gilbert See,
Nicholas Wiswell,
Masaya Kawano
2021 IEEE 71st Electronic Components and Technology Conference (ECTC)
12 May 2021
SERC
Institute of Microelectronics
Technology Trends in 2.5D/3D Packaging and Heterogeneous Integration
Masaya Kawano
2021 5th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)
1 Nov 2017
SERC
Institute of Microelectronics
Study on Low Warpage and High Reliability for Large Package Using TSV-Free Interposer Technology Through SMART Codesign Modeling
Mian Zhi Ding,
Yong Han,
Surya Bhattacharya,
Fa Xing Che,
Masaya Kawano
IEEE Transactions on Components, Packaging and Manufacturing Technology
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