Assembly process characterization of 3D Stacking of Heterogeneous Chiplets

Assembly process characterization of 3D Stacking of Heterogeneous Chiplets

2023 IEEE 25th Electronics Packaging Technology Conference (EPTC)

10.1109/EPTC59621.2023.10457705

http://dx.doi.org/10.1109/eptc59621.2023.10457705

Sharon Pei Siang Lim, Boon Long Lau, Tai Chong Chai, Yong Liang Ye

18 March 2024

Siang Lim, S. P., Long Lau, B., Chai, T. C., & Liang Ye, Y. (2023, December 5). Assembly process characterization of 3D Stacking of Heterogeneous Chiplets. 2023 IEEE 25th Electronics Packaging Technology Conference (EPTC). https://doi.org/10.1109/eptc59621.2023.10457705

The demands of advanced electronics products such as Automotive Radar and High functionality Smartphones have driven the growth of RF packaging market especially in radio frequency (RF) applications. Hence there is a need for RF devices with smaller form factors and higher speed operation. In this work, we have successfully demonstrated an assembly approach of CMOS and RF device chiplets stacked in a 3D configuration on a modified FOWLP platform. The chip-to-wafer bonding and different assembly processes will be discussed in the paper. The TSV measurement results and the daisy chain measurement results will also be updated.

Publisher Copyright

This research is supported by core funding from: High Density SiP Consortium for Heterogeneous Chiplets Integration
Grant Reference no. : NA

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