Cu and barrier CMP process development with fine 1μm Cu bond pad and 2.5 μm pitch for Wafer-to-wafer Hybrid Bonding

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Cu and barrier CMP process development with fine 1μm Cu bond pad and 2.5 μm pitch for Wafer-to-wafer Hybrid Bonding
Title:
Cu and barrier CMP process development with fine 1μm Cu bond pad and 2.5 μm pitch for Wafer-to-wafer Hybrid Bonding
Journal Title:
2023 IEEE 25th Electronics Packaging Technology Conference (EPTC)
Keywords:
Publication Date:
18 March 2024
Citation:
Roy, S. C., Guan, C. G., Venkataraman, N., Lee, W., & Singh, N. (2023, December 5). Cu and barrier CMP process development with fine 1μm Cu bond pad and 2.5 μm pitch for Wafer-to-wafer Hybrid Bonding. 2023 IEEE 25th Electronics Packaging Technology Conference (EPTC). https://doi.org/10.1109/eptc59621.2023.10457780
Abstract:
Fine pitch hybrid bonding is evolving as a vital advanced permanent bonding in 3D IC technology for its low cost and providing shorter global interconnect length. Chemical mechanical planarization (CMP) is a critical process step for realizing uniform Cu dishing control all over the wafer for successful W2W hybrid bonding. In this paper, we have investigated the effect of various CMP conditions using a three- step CMP process, on Cu dishing, intra-die oxide planarity, and surface roughness and have attempted to understand the dishing control mechanism for our developed CMP process. Atomic force microscopy has been used to characterize the dishing and non-uniformity of the wafers. We have demonstrated controlled dishing <3 nm, intra-die oxide planarity <0.6 nm, and Cu/oxide surface roughness <0.3 nm for 1 µm Cu bond pad size and fine pitch ~2.5µm. Our analysis indicates that the balanced combination of HPP and LPP with polish time control for Cu and barrier polishing helps to control the Cu pad dishing and achieve high uniformity all over the wafer. Our study outlines a way for the optimization of Cu and barrier CMP processes for fine-pitch Cu pads for hybrid bonding applications.
License type:
Publisher Copyright
Funding Info:
This research / project is supported by the GlobalFoundries Singapore - Stacked BSI Sensor Project
Grant Reference no. : NA
Description:
© 2024 IEEE.  Personal use of this material is permitted.  Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
ISSN:
979-8-3503-2957-5
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