Lin, Z., Guan, L. T., Jiaqi, W., Feng, X., Chinq, J. M., & Chyn, N. Y. (2023, December 5). Parasitic Surface Conduction Effect of TSV on Interconnection Performance in RF SOI for 2.5D Integration. 2023 IEEE 25th Electronics Packaging Technology Conference (EPTC). https://doi.org/10.1109/eptc59621.2023.10457708
Abstract:
Silicon interposer is being widely used for 2.5D
integration due to its advanced performance. However, the resistivity of the silicon can be
impacted by the parasitic surface conduction (PSC) near the Si-SiO2 interface, especially for
the space around through silicon vias (TSVs) where trap-rich layer cannot be created to alleviate
the PSC effect. In this paper, the PSC effect of the TSV on the interconnection performance in a RF
silicon on insulator (SOI) wafer is analyzed. A TSV GSG connection with a thin
effective-resistivity layer of different resistivities presenting the low resistivity introduced by
the PSC effect is simulated and analyzed. Moreover, a series of test structures is
fabricated on a RF SOI wafer. The S parameters are measured and lumped RLGC parameters are
analyzed. The simulated and measured results both demonstrate an increased loss of the TSV
connection. The results are useful for future high-
performance 2.5D integration design.
License type:
Publisher Copyright
Funding Info:
This research / project is supported by the National Research Foundation, Singapore - Singapore Hybrid-Integrated Next-Generation µ-Electronics (SHINE) Centre Funding Programe
Grant Reference no. : N/A