Chia, L. Y., Bhuvanendran Nair Gourikutty, S., & Ho, S. W. (2023, December 5). Solutions for Process Challenges on Fan-Out Wafer Level Packaging of Electronic-Photonic Integration. 2023 IEEE 25th Electronics Packaging Technology Conference (EPTC). https://doi.org/10.1109/eptc59621.2023.10457673
Abstract:
The integration of electronic and photonic components on
the same package is gaining more significance in fields such as high-performance computing and
hyper-scale data centres for high bandwidth communication, reducing power consumption, and
improving overall system performance. Here, a Mold first Fan-out Wafer Level Packaging was chosen
to integrate a Photonic Integrated Circuit Chip consisting of special structures such as
cavities together with other electronic Integrated Circuit Chips. Few process challenges are
encountered in this development for embedding Photonic Integrated Circuit Chip and other ICs inside
mold, such as (a) Molding tape residue inside the cavity during the reconstitution process
(b) Dielectric layers coverage on Epoxy Mold Compound at the area between Photonic Integrated
Circuit Chip and other adjacent Integrated Circuit Chip, (c) Photoresist coverage at cavity area.
This study explores resolutions to tackle the aforementioned process challenges
during fabrication.
License type:
Publisher Copyright
Funding Info:
This research / project is supported by the A*STAR - Science and Engineering Research Council (SERC) - N/A
Grant Reference no. : 12001E0071