Multi-Chiplet Heterogeneous Integration Packaging for Semiconductor System Scaling

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Multi-Chiplet Heterogeneous Integration Packaging for Semiconductor System Scaling
Title:
Multi-Chiplet Heterogeneous Integration Packaging for Semiconductor System Scaling
Journal Title:
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)
Keywords:
Publication Date:
24 July 2023
Citation:
Bhattacharya, S., & Rao, V. S. (2023, June 11). Multi-Chiplet Heterogeneous Integration Packaging for Semiconductor System Scaling. 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits). https://doi.org/10.23919/vlsitechnologyandcir57934.2023.10185396
Abstract:
Since the invention of the transistor, we have enjoyed tremendous impact of semiconductors on electronic systems. Transistor scaling has played a critical role in achieving increased functionality of semiconductor systems in main-frames, personal computers, and mobile phones by enabling lower power, cost and area per function through monolithic System-on-Chip (SoC). However, over the past decade, the diverse system requirements from wide ranging markets have driven the industry to use heterogeneous integration of multiple chiplets enabled by advanced packaging as a key new toolbox for System-in-Package scaling. This paper provides an overview of multi-chiplet heterogeneous integration (MCHI) packaging platforms to address system scaling needs in coming decades.
License type:
Publisher Copyright
Funding Info:
There was no specific funding for the research done
Description:
© 2023 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
ISSN:
2158-9682
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