Bhattacharya, S., & Rao, V. S. (2023, June 11). Multi-Chiplet Heterogeneous Integration Packaging for Semiconductor System Scaling. 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits). https://doi.org/10.23919/vlsitechnologyandcir57934.2023.10185396
Abstract:
Since the invention of the transistor, we have enjoyed tremendous impact of semiconductors on electronic systems. Transistor scaling has played a critical role in achieving increased functionality of semiconductor systems in main-frames, personal computers, and mobile phones by enabling lower power, cost and area per function through monolithic System-on-Chip (SoC). However, over the past decade, the diverse system requirements from wide ranging markets have driven the industry to use heterogeneous integration of multiple chiplets enabled by advanced packaging as a key new toolbox for System-in-Package scaling. This paper provides an overview of multi-chiplet heterogeneous integration (MCHI) packaging platforms to address system scaling needs in coming decades.
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Publisher Copyright
Funding Info:
There was no specific funding for the research done