Zang, Q., Goh, W. L., Lu, L., Yu, C., Mu, J., Kim, T. T.-H., Kim, B., Li, D., & Do, A. T. (2023, May 21). 282-to-607 TOPS/W, 7T-SRAM Based CiM with Reconfigurable Column SAR ADC for Neural Network Processing. 2023 IEEE International Symposium on Circuits and Systems (ISCAS). https://doi.org/10.1109/iscas46773.2023.10181435
Abstract:
Compute in memory ( C iM) is a promising solution for solving the bottleneck of frequent data interface between memory and processor in Von-Neumann architecture. In this work, a hybrid current/charge domain 7T-SRAM based CiM architecture is proposed to mitigate the PVT-induced RBL variation during computation and thus offer a better linearity without significant impact on the operating frequency and area efficiency. Additionally, a column-referenced 1b to 5b reconfigurable SAR ADC is proposed to support multi-bit output. The proposed design is verified by the Monte-Carlo simulations using 40nm CMOS technology. The 5b mode ADC transferred MAC curve's DNL (LSB) ranges from −0.025 to 0.02 and INL (LSB) ranges from −0.13 to 0.25. The largest RBL variation (σ) from MAC value −64 to MAC value +64 is 2.08 mV, resulting in a MNIST classification accuracy of 97.5%, which is only 0.1% degradation and Google Speech Command classification accuracy of 80.5%, which is only 0.5% degradation compared to the software baseline, respectively. The whole architecture offers energy efficiency of 282-to-607 TOPS/W for 1-5b output in the MAC operation, which is competitive when compared to other state-of-art C iM architectures.
License type:
Publisher Copyright
Funding Info:
This research / project is supported by the A*STAR - Spin-Orbit Technologies for intelligence at the Edge (SpOT-LITE)
Grant Reference no. : A18A6b0057