Doping-selective etching of silicon for wafer thinning in the fabrication of backside-illuminated stacked CMOS image sensors

Doping-selective etching of silicon for wafer thinning in the fabrication of backside-illuminated stacked CMOS image sensors

2023 IEEE 73rd Electronic Components and Technology Conference (ECTC)

10.1109/ECTC51909.2023.00259

http://dx.doi.org/10.1109/ectc51909.2023.00259

Nandini Venkataraman, Benedikt Risse, Gregorio Decierdo, Navab Singh, Darshini Senthilkumar, Deepthi Kandasamy, Eng Huat Toh, Louis Lim

03 August 2023

Venkataraman, N., Risse, B., Decierdo, G., Singh, N., Senthilkumar, D., Kandasamy, D., Toh, E. H., & Lim, L. (2023, May). Doping-selective etching of silicon for wafer thinning in the fabrication of backside-illuminated stacked CMOS image sensors. 2023 IEEE 73rd Electronic Components and Technology Conference (ECTC). https://doi.org/10.1109/ectc51909.2023.00259

Backside illuminated (BSI) 3D stacked CMOS image sensors are of significant interest for various applications including light detection and ranging (LiDAR). One of the important challenges in the 3D integration of these devices involves well-controlled backside thinning of the single photon avalanche diode (SPAD) wafers, which are stacked with CMOS wafers. Backside wafer thinning is usually accomplished by a combination of backgrinding and doping-sensitive wet chemical etching of silicon. In this study, we have developed a wet etch process based on tailored HF : HNO 3 :CH 3 COOH (HNA) chemistries, capable of achieving etch stop at a p+/p silicon transition layer with high doping-level selectivity (>90: 1). Feasibility of excellent total thickness variation of ~300 nm is demonstrated across a 300 mm wafer. In addition, well-known properties of HNA-etched silicon surfaces including staining and surface roughness are characterized. Finally, a wet chemical tip-etch method for reducing surface roughness is proposed.

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2377-5726

Institute of Microelectronics