High-Performance Amplifier Package Design for Heterogenous Integration on Si-interposer

High-Performance Amplifier Package Design for Heterogenous Integration on Si-interposer

2023 IEEE 73rd Electronic Components and Technology Conference (ECTC)

10.1109/ECTC51909.2023.00315

http://dx.doi.org/10.1109/ectc51909.2023.00315

Teck Guan Lim, Lin Zho, Sasi Kumar Tippabhotla, Ji Lin, Jong Ming Chinq, Jiaqi Wu, Tang Gongyue, Eva Wai Leong Ching, Yong Chyn Ng, King Jien Chui, Wei Jia Lu, Chee Heng Goh, Sek Lin Pek, Jun Wei Agnes Loh

03 August 2023

Lim, T. G., Zho, L., Tippabhotla, S. K., Lin, J., Chinq, J. M., Wu, J., Gongyue, T., Ching, E. W. L., Ng, Y. C., Chui, K. J., Lu, W. J., Goh, C. H., Lin Pek, S., & Loh, J. W. A. (2023, May). High-Performance Amplifier Package Design for Heterogenous Integration on Si-interposer. 2023 IEEE 73rd Electronic Components and Technology Conference (ECTC). https://doi.org/10.1109/ectc51909.2023.00315

The RF design for the wire bond and flip-chip Power Amplifier (PA) MMIC on the High Resistivity (HiR) Si-interposer are presented in this paper. The HiR Si-interposer is to support multiple off-the-shelf RF and Baseband ICs for complex advanced RF frontend modules using heterogeneous integration. A two-sided thermal cooling solution is adopted for this high-performance integration architecture. The high-power dissipation MMIC is integrated using flip-chip assembly so that the heat can be dissipated through the top heat spreader. For the other ICs, they are integrated using wire bond assembly so that their heat will be dissipated through the bottom HiR Si-interposer.

Publisher Copyright

This research / project is supported by the National Research Foundation (NRF) - Singapore Hybrid-Integrated Next-Generation μ-Electronics (SHINE) Centre funding programme
Grant Reference no. : NA

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Institute of Microelectronics