Zhang, L., Raju, S., James, A., Dutta, R., Fournier, G., Lancry, D., Chuan, K. C. T., Chandrasekhar, V. R., & Foo, C. S. (2022). Bayesian Deep Active Learning for Analog Circuit Performance Classification. 2022 IEEE International Symposium on Circuits and Systems (ISCAS). https://doi.org/10.1109/iscas48785.2022.9937416
Computationally intensive simulations have made analog circuit sizing challenging for complicated analog circuit performance characterization. Accurate yet computationally efficient data-driven models of circuit performance can potentially accelerate the design and verification process. However, as analog circuits are designed under strict functional and technology constraints, there is a scarcity of data for analog circuit performance classification, posing challenges to data-driven approaches; acquiring more data typically involves running expensive and time consuming simulations. We propose Bayesian Deep Active Learning (BDAL) to learn models using fewer simulations, by iteratively selecting a small number of informative samples to label based on the model uncertainty. Bayesian neural networks used in the BDAL framework are better able to model weight uncertainty while being sufficiently expressive to model complex circuits. Compared with the state-of-the-art approaches, the proposed BDAL method can obtain better classification performance with much fewer number of simulations. Experiments on four diverse analog circuits demonstrate BDAL can achieve significant reduction in data requirement and obtain similar performance with much less labeled data for analog circuit performance classification.
This research / project is supported by the Agency for Science, Technology and Research (A*STAR) - AME Programmatic Funds
Grant Reference no. : A20H6b0151