Mechanical modeling study for fan-out wafer level package parameters to enhance BGA TCoB life

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Mechanical modeling study for fan-out wafer level package parameters to enhance BGA TCoB life
Title:
Mechanical modeling study for fan-out wafer level package parameters to enhance BGA TCoB life
Journal Title:
2021 IEEE 23rd Electronics Packaging Technology Conference (EPTC)
Keywords:
Publication Date:
05 January 2022
Citation:
Mandal, R., & Chong, C. T. (2021). Mechanical modeling study for fan-out wafer level package parameters to enhance BGA TCoB life. 2021 IEEE 23rd Electronics Packaging Technology Conference (EPTC). https://doi.org/10.1109/eptc53413.2021.9663967
Abstract:
Fan-Out Wafer Level Package (FOWLP) is experiencing a significant growth due to its thinner thickness, higher I/Os in smaller chip area, better thermal and electrical performance. Due to the shorter, finer and simpler interconnection as compare to flip chip, FOWLP shows superior performance. On the other hand this package is vulnerable due to its higher warpage and package stress concentration. This paper will explore different options to enhance board level reliability performance during temperature cycling for FOWLP. The mechanical simulation has been performed for board level temperature cycling reliability test on a uniform ball pitch, with/without UBM (under bump metallization), BGA with underfill, SACQ (bismuth bearing SnAgCu alloy) solder material and different package design factors (pad diameter, solder resist opening, silicon chip thickness, BGA height, etc). Our aim from this mechanical simulation is to find ways to enhance TCoB (temperature cycling on board) solder joint life performance for FOWLP to be used for antenna-in-package (AiP) automotive radar application. Among the different package parameters, UBM, SACQ solder, solder resist opening and larger BGA height are the few packaging parameters which significantly enhancing the BGA solder joint life. The most noticeable factor bismuth bearing SACQ shows more than 2x performance improvement whereas underfilling the BGA layer in the FOWLP package reduces solder join life significantly.
License type:
Publisher Copyright
Funding Info:
This research is supported by core funding from: Institute of Microelectronics (IME)
Grant Reference no. : NIL
Description:
© 2022 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
ISBN:
978-1-6654-1619-1
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