Han, Y., & Kawano, M. (2021). Thermal Effect Investigation of Chip-to-Wafer Hybrid Bonding on 3D-Stacked Memory. 2021 IEEE 23rd Electronics Packaging Technology Conference (EPTC). https://doi.org/10.1109/eptc53413.2021.9663907
Chip-to-Wafer (C2W) hybrid bonding, which includes Cu/SiO 2 interconnection interfaces, has been foreseen as an essential technology for future memory stacking success. The heat conduction capability of hybrid interconnection bonding interface will represent a significant affecting factor to the main thermal path, especially in the package of multiple chips stacked together. In this work, a 4-layer memory stack will be fabricated in C2W hybrid bonding process with Cu/SiO 2 interconnection interfaces. Three main types bonding structures of different pad diameters and pitches will be considered for the prototype design. Thermal simulation models with detailed structure and dimension have been constructed to analyze the heat conduction performance of hybrid bonding layer. Thermal resistance of Grp 3 bonding structure is 2.49°Cmm 2 /W, and the equivalent thermal conductivity is 4.2W/mK. Simulation analyses have been performed on other interconnection structures and materials for thermal performance comparison. At package level, thermal resistances have been evaluated for different cases. The obtained investigation results are expected to aid the thermal design of 3D-stacked memories for high performance applications.
This research is funded by Chip to Wafer Hybrid Bonding Consortium