Heterogeneous Integration on Fan-Out Wafer Level Packaging Platform

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Heterogeneous Integration on Fan-Out Wafer Level Packaging Platform
Title:
Heterogeneous Integration on Fan-Out Wafer Level Packaging Platform
Journal Title:
2021 IEEE 23rd Electronics Packaging Technology Conference (EPTC)
Keywords:
Publication Date:
05 January 2022
Citation:
Chai, T., Ho, D., Chong, S., Sharon Lim, P., Hsiao, H., & Soh, J. (2021). Heterogeneous Integration on Fan-Out Wafer Level Packaging Platform. 2021 IEEE 23rd Electronics Packaging Technology Conference (EPTC). https://doi.org/10.1109/eptc53413.2021.9663922
Abstract:
This paper provides an update on projects undertaken in the FOWLP development line namely the AiP in FOWLP for mmWave Radar Consortium and the newly launched Chiplet Consortium. Some of notable process development on RDL technologies being developed for heterogeneous integration high density chiplet packaging and multi-layer wafer level mold encapsulation capabilities will also be updated.
License type:
Publisher Copyright
Funding Info:
This research / project is supported by the A*STAR - IPP-IAF - Fan-Out Wafer-Level-Packaging (FO-WLP) Development Line - 1528100051
Grant Reference no. : 1528100051
Description:
© 2022 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
ISBN:
978-1-6654-1619-1
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