Wang, X., Kawano, M., & Chandra Rao, B. S. S. (2021). Silicon Isolation Trench Integration for the 4-stack Memory Wafer. 2021 IEEE 23rd Electronics Packaging Technology Conference (EPTC). https://doi.org/10.1109/eptc53413.2021.9663912
Abstract:
Transistor technology node has reached 5nm to 7nm in scaling, with on-going research efforts to shrink to down 2nm. However, transistor scaling faces physical limitation in terms of performance parity. 3D IC packaging provides an alternative possibility to enhance its overall system/package level performance. Several approaches are studied to realize 3D IC packages for performance improvement. One of them is “one-step through-silicon-via (TSV)” [1] for 3D stacked memory module applications. In this approach, one critical process is fabrication of the silicon isolation trench. The silicon isolation trench process flow [2] and the yield improvement actions have been discussed [3]. However, results in these previous works are based on 2-stack memory wafers. This paper reports the fabrication challenges of Si isolation trench for 4-stack memory wafers, and provides some of the solutions to the challenges and issues.