Dutta, R., James, A., Raju, S., Jeon, Y.-J., Foo, C. S., & Tshun Chuan Chai, K. (2022). Automated Deep Learning Platform for Accelerated Analog Circuit Design. 2022 IEEE 35th International System-on-Chip Conference (SOCC). https://doi.org/10.1109/socc56010.2022.9908139
Abstract:
We present an analog design framework for circuit sizing selection using neural networks. The proposed automated deep learning (ADL) platform uses neural networks (NN) as a differentiable surrogate model for circuit performance to model the nonlinear and high dimensional relationships between sizing performance and circuit performance in analog circuits. Gradient-based constrained optimization is then used to propose new sizing parameters for the desired design closure, which are then verified using EDA tools. If circuit performance falls short of desired performance, the simulation results from the EDA tools are also used as additional training data to update the neural network model for the next design iteration. The tight coupling between NN and EDA tools in an iterative design loop achieves multi-variate design closure and has the capability to synthesize circuits with a significantly reduced number of circuit simulations.
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Funding Info:
This research / project is supported by the A*STAR - AME Programmatic Fund
Grant Reference no. : A20H6b0151
This research / project is supported by the A*STAR - AME Programmatic Fund
Grant Reference no. : A19E8b0102