Ji, L., Kawano, M., Tippabhotla, S. K., & Loh, W. L. (2021). Numerical study on wafer level warpage evolution during chip to wafer hybrid bonding process. 2021 IEEE 23rd Electronics Packaging Technology Conference (EPTC). https://doi.org/10.1109/eptc53413.2021.9663908
Abstract:
A Finite Element Analysis (FEA) modelling study on process-dependent wafer warpage during chip to wafer hybrid bonding (C2W-HB) process is presented in this paper. The test vehicle includes a top high density (HD) package with multi-stacking dies and a bottom TSV wafer. Two types of dielectric materials, i.e. SiO 2 and polymer, are considered for hybrid bonding. Due to the unbalanced structure for this C2W-HB test vehicle, high warpage is predicted after the bonded wafer being detached from glass carrier. The numerical study shows some evidence that using SiO 2 instead of EMC to encapsulate the top package may be the potential option to reduce wafer warpage. The parametric study on through silicon via (TSV) area density and TSV thickness also help enhance the understanding of the possible options to mitigate large wafer warpage during C2W process.
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Publisher Copyright
Funding Info:
There was no specific funding for the research done