Yu, C., Chuan Chai, K. T., Kim, T. T.-H., & Kim, B. (2021). A Zero-Skipping Reconfigurable SRAM In-Memory Computing Macro with Binary-Searching ADC. ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC). https://doi.org/10.1109/esscirc53450.2021.9567819
This work proposes a reconfigurable SRAM in-memory computing macro for processing neural networks using a pair of 7T bitcells. The proposed dual 7T bitcell structure decouples the read operation and offers a reconfigurable weight precision (3–15 levels). It also saves computing energy by skipping zeros for both weights and input activations. A 528×128 dual 7T bitcell array is constructed for the massively parallel 128 dot-products between reconfigurable precision weights (1.6-3.9bit) and binary inputs. A column consists of 384 bitcells for dot-products, 96 bitcells for ADC, and 48 bitcells for offset calibration. The bitcells for the column-by-column binary searching ADC are divided into two groups, each with 48 bitcells having fixed ‘+1’ or ‘-1’ weight. The column ADC then converts an analog dot-product result into a 5-7bit digital output code by dynamically changing the reference level through controlling the inputs for the 96 replica bitcells. A test-chip is fabricated using 65nm and the proposed bitcell array occupies 0.378mm 2 . The energy efficiency of a unit multiply-and-accumulate (MAC) operation is 258.5/67.9/23.9TOPS/W at 1.6/2.8/3.9bit weight using 0.45/0.8V supply voltages and 200MHz operating clock frequency.
This research is supported by core funding from: Institute of Microelectronics
Grant Reference no. : N.A.