An, K.-C., Narasimman, N., & Kim, T. T.-H. (2021). A 0.6-to-1.2 V Scaling Friendly Discrete-Time OTA-Free ΔΣ-ADC for IoT Applications. ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC). https://doi.org/10.1109/esscirc53450.2021.9567788
Abstract:
This work presents a scaling-friendly Discrete-Time (DT) 2 nd order ΔΣ ADC using a passive switched capacitor (SC) integrator and a novel VCO-Frequency Delta-Sigma Modulator (FDSM). The proposed VCO-FDSM employs a linear VCO with negative feedback. A novel all-digital frequency quantizer quantizes the VCO frequency into a multibit output with inherent dynamic element matching (DEM) property, which provides the 1 st order mismatch noise shaping in the feedback DAC. The passive SC integrator at the input provides an additional order of noise shaping to the VCO-FDSM. This highly digital architecture facilitates a trade-off between the supply voltage and the operational bandwidth (BW) and makes the design suitable for energy-efficient IoT applications. The test chip fabricated in 65nm CMOS technology operates at the supply voltages ranging from 0.6 V to 1.2 V and achieves a 75.7dB peak SNR in 3.5kHz BW, consuming 7.78 µW with a FoMs of 162.2dB at a 1V supply voltage.
License type:
Publisher Copyright
Funding Info:
This research / project is supported by the A*STAR - Programmatic - Ultrasonic Wavefront Computing
Grant Reference no. : A19E8b0102