FOWLP and Si-Interposer for High-Speed Photonic Packaging

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FOWLP and Si-Interposer for High-Speed Photonic Packaging
Title:
FOWLP and Si-Interposer for High-Speed Photonic Packaging
Journal Title:
2021 IEEE 71st Electronic Components and Technology Conference (ECTC)
Publication Date:
10 August 2021
Citation:
Guan, L. T., Ching, E. W. L., Ching, J. M., Leng, L. W., Wee, D. H. S., & Bhattacharya, S. (2021). FOWLP and Si-Interposer for High-Speed Photonic Packaging. 2021 IEEE 71st Electronic Components and Technology Conference (ECTC). https://doi.org/10.1109/ectc32696.2021.00050
Abstract:
A FOWLP and a Si-Interposer integration platform for Electronic IC (EIC) and Photonic IC (PIC) are described here. These two platforms are capable to support high-speed integration and scalable design of the next generation Optical Engine. The integration of the PIC on the FOWLP is achieved by a simple novel solution. An additional section of the Si substrate is designed at the end of the PIC to protect the optical I/Os during the FOWLP embedding process. For the Through Si-Interposer, besides providing the EIC and PIC, it include the passive alignment feature for the fibre to the PIC assembly.
License type:
Publisher Copyright
Funding Info:
This research / project is supported by the A*STAR - GAP
Grant Reference no. : ETPL/18-GAP056-R20A
Description:
© 2021 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
ISSN:
2377-5726
ISBN:
978-1-6654-4097-4
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