The Design of CMOS-Compatible Plasmonic Waveguides for Intra-Chip Communication

The Design of CMOS-Compatible Plasmonic Waveguides for Intra-Chip Communication

IEEE Photonics Journal

10.1109/JPHOT.2020.3024119

http://dx.doi.org/10.1109/jphot.2020.3024119

Yan Liu, Lu ding, Yu Cao, Dongyang Wan, Guanghui Yuan, Baohu Huang, Aaron Voon-Yew Thean, Ting Mei, Thirumalai Venkatesan, Christian A. Nijhuis, Soojin Chua

Electrical and Electronic Engineering, Atomic and Molecular Physics, and Optics

16 September 2020

Liu, Y., Ding, L., Cao, Y., Wan, D., Yuan, G., Huang, B., Voon-Yew Thean, A., Mei, T., Venkatesan, T., Nijhuis, C. A., & Chua, S. (2020). The Design of CMOS-Compatible Plasmonic Waveguides for Intra-Chip Communication. IEEE Photonics Journal, 12(5), 1–10. https://doi.org/10.1109/jphot.2020.3024119

A CMOS-compatible plasmonic waveguide with a metal or metal-like strip sandwiched in-between dielectrics has been proposed for intra-chip communication in the more-than-Moore era. A sequence of numerical models has been presented to evaluate the plasmonic waveguide performance. For device-level consideration, we demonstrated through simulations that Cu (1450 nm pitch) and PLD-TiN (900 nm pitch) plasmonic waveguides symmetrically sandwiched by SiO 2 with much smaller and hence denser interconnects, are promising candidates for use in global wires for the asynchronous communication. This design of plasmonic waveguide can bridge the CMOS circuitry and high-speed communication at optical frequencies within chip. For a system-level assessment, both of them have the same bandwidth throughput of ~19.8 Gbps. The other performance parameters of Cu and PLD-TiN plasmonic waveguides are respectively, signal latency of ~0.18 ps and 0.19 ps, energy dissipation per computing bit of ~2.5 × 10 -3 fJ/bit and 3.8 × 10 -3 fJ/bit, and 25% crosstalk coupling length of 155 μm and 125 μm. These findings suggest that plasmonic waveguide for intra-chip communication surpass those of existing electronic interconnects for all the categories of performance parameters.

Attribution 4.0 International (CC BY 4.0)

This research / project is supported by the National Research Foundation Singapore - Integration of Electrically Driven Plasmonic Components in High Speed
Grant Reference no. : NRF2016_CRP001_111

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https://oar.a-star.edu.sg/communities-collections/articles/18342

1943-0655
1943-0647

Institute of Materials Research and Engineering

http://dx.doi.org/10.1109/jphot.2020.3024119