One-step TSV process development for 4-layer wafer stacked DRAM

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One-step TSV process development for 4-layer wafer stacked DRAM
Title:
One-step TSV process development for 4-layer wafer stacked DRAM
Journal Title:
2021 IEEE 71st Electronic Components and Technology Conference (ECTC)
Keywords:
Publication Date:
10 August 2021
Citation:
Kawano, M., Wang, X.-Y., Ren, Q., Loh, W.-L., Rao, BSS. C., & Chui, K.-J. (2021). One-step TSV process development for 4-layer wafer stacked DRAM. 2021 IEEE 71st Electronic Components and Technology Conference (ECTC). https://doi.org/10.1109/ectc32696.2021.00117
Abstract:
The 3D stacked DRAM is an essential key module for high-performance computing systems. However, the cost increase due to 3D stacking limits its applications. The current 3D stacking technology requires front-side and backside microbumps, temporary bonding and debonding, time-consuming chip stacking etc., as additional process steps. In this paper, a 4-layer one-step TSV fabrication process is studied, enabling only one-time TSV fabrication combined with bumpless wafer-to-wafer stacking. Multi-stack layer dry etching is successfully demonstrated with photoresist masks by optimizing Si, oxide, and Al etching. Sidewall angles were controlled in the order of Si > SiO 2 > Al to balance aspect ratio and TSV/Al-pad connection. Cu filling is done by electroplating, and right filling property and good contact between Al sidewall and TSV are confirmed by cross-sectional analysis.
License type:
Publisher Copyright
Funding Info:
There was no specific funding for the research done
Description:
© 2021 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works
ISBN:
978-1-6654-3120-0
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