3D Cryogenic Interposer for Quantum Computing Application

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3D Cryogenic Interposer for Quantum Computing Application
Title:
3D Cryogenic Interposer for Quantum Computing Application
Journal Title:
2022 IEEE 72nd Electronic Components and Technology Conference
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Publication Date:
04 October 2021
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Abstract:
Quantum computing gathered a lot of attention since IBM started promoting quantum computing via cloud in 2016. Since then, many companies are now furthering work on the qubit development and integration technologies, and a 3D cryogenic interposer is one such technology that can provide the integration platform for qubit and thus realise practical devices for quantum computing applications. In this work, we report preliminary testing results of a Si interposer with embedded through silicon via (TSV) (5×50 µm) and Al metal lines at cryogenic temperatures down to 20 mK. The embedded TSV was fabricated by 300mm conventional TSV line. 300 mm Si substrate was used for TSV fabrication. A SiO2 hard mask was deposited on Si substrate and this is followed by pattern of 5µm diameter TSV on the Si hard mask. BOSCH etch process was used for the TSV drilling in the Si substrate. Photoresist strip and wet clean were processed after 50 µm TSV etching. Ozone/TEOS (tetraethoxysilane) was conformably deposited in the TSV as the liner to electrically isolate TSV from the Si substrate. Ta and Cu were sputter deposited in the TSV as barrier and Cu seed respectively in a PVD system. Bottom up electroplating was then used to solid fill the TSV. TSV annealing was conducted in the furnace after ECP. Cu CMP was done for the planarization of TSV and isolate it from the top surface. Ti/Al were sputter deposited on top of TSV for the electrical connection of TSV. Al metal pads and lines were masked and etched. Finally, the TSVs and metal lines were singled and assembled on the cryogenic board (daughter board) for the testing. Au wire was used to connect the Al pad to the cryogenic board (daughter board) before the daughter board with the mounted sample was fixed on the cryogenic mother board (QDevil). The mother board with the sample was loaded into the dilution refrigerator. The electrical measurements were conducted when the refrigerator was cooled down to 4 K and 20 mK. The performances of the TSV and metal line were further characterised when the sample was warmed up to room temperature (RT). The capacitance of TSV was reduced when temperature was cooled from RT to 4 K. The capacitance did not change when the temperature further reduced to 20 mK based on the current data. The leakage of TSVs was < 1.7 E-7A and stable to thermal cycling. To measure the superconducting transition of Al, 1 µm thickness Al line with 250 Å Ti barrier layer sample was fabricated, assembled and tested in the dilution refrigerator. The resistance of Al line was reduced from 5 Ohm to ~0.3 Ohm when the temperature cooled down from RT to 1.35 K, and we measured the superconducting transition temperature to be at 1.12 K. The resistance was further reduced less than 0.1 Ohm. Cross-section scanning electron micrographs (SEM) of the TSV was prepared by focused ion beam (FIB) after the sample was warmed up to room temperature. The liner oxide of the TSV was intact without delamination in the cross-section SEM. The leakage current (< 1.7E-7A) was unchanged after sample warmed up, from which we can conclude that the TSV liner is robust to thermal cycling and Al line is a promising metal to use for interconnects for quantum computing application. In summary, we characterized the superconducting performance of the Al line in this paper. The performance of conventional TSVs used and the superconducting Al line are potentially useful for forming the basic components in a 3D cryogenic interposer for applications in quantum computing.
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Publisher Copyright
Funding Info:
This research / project is supported by the A*STAR - Delta-Q Strategic Research Programme
Grant Reference no. : C210917001
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