Transfer Learning-Based Artificial Intelligence-Integrated Physical Modeling to Enable Failure Analysis for 3 Nanometer and Smaller Silicon-Based CMOS Transistors

Transfer Learning-Based Artificial Intelligence-Integrated Physical Modeling to Enable Failure Analysis for 3 Nanometer and Smaller Silicon-Based CMOS Transistors

ACS Applied Nano Materials

10.1021/acsanm.1c00960

https://doi.org/10.1021/acsanm.1c00960

Jieming Pan, Kain Lu Low, Joydeep Ghosh, Senthilnath Jayavelu, Md Meftahul Ferdaus, Shang Yi Lim, Evgeny Zamburg, Yida Li, Baoshan Tang, Xinghua Wang, Jin Feng Leong, Savitha Ramasamy, Tonio Buonassisi, Chen-Khong Tham, Aaron Voon-Yew Thean

Transfer Learning, Machine Learning, failure analysis, transistor bridge defect, CMOS, FinFET, GAAFET, technology computer-aided design (TCAD)

28 June 2021

Pan, J., Low, K. L., Ghosh, J., Jayavelu, S., Ferdaus, M. M., Lim, S. Y., … Thean, A. V.-Y. (2021). Transfer Learning-Based Artificial Intelligence-Integrated Physical Modeling to Enable Failure Analysis for 3 Nanometer and Smaller Silicon-Based CMOS Transistors. ACS Applied Nano Materials, 4(7), 6903–6915. doi:10.1021/acsanm.1c00960

Integral to the success of the semiconductor industry in keeping up with Moore’s law is the importance of failure analysis. Accurate and fast failure analysis is vital in ensuring yield, reliability, and rapid production in the semiconductor industry. However, locating defects among tens of billions of transistors packed in the tiny modern microchip is not a trivial task. Not only has the process technology to achieve such high integration of devices evolved to become astoundingly sophisticated, debugging for defects in these chips has also become remarkably complex. With electrical nanoprobing, we show how artificial intelligence-integrated physical modeling can be effective in finding difficult proverbial needle-in-a-haystack defects based on the electrical responses of the devices. Moreover, the information learned on current devices can be transferred to the latest transistor technologies, enabling machine-learning-based defect sleuths of the future. Notably, we achieved a defect region classification accuracy of 99.5% on well-studied fin nanoscale field-effect transistors using a defect dataset based on an experimentally calibrated TCAD digital twin model and an adaptive boundary refinement technique. With transfer learning, a defect region classification accuracy of 99.58% is also achieved on the next-generation gate-all-around field-effect transistors, overcoming the lack of crucial datasets and optimized labels to guide and accelerate the production process of emerging devices. The proposed technique is expected to be the next level of defect identification, an important stepping stone to accelerate the production process for advanced technology nodes beyond 3nm.

Publisher Copyright

This research / project is supported by the Accelerated Materials Development for Manufacturing Program at A*STAR - AME Programmatic Fund
Grant Reference no. : A1898b0043

This document is the Accepted Manuscript version of a Published Work that appeared in final form in ACS Applied Nano Materials, copyright © American Chemical Society after peer review and technical editing by the publisher. To access the final edited and published work see https://doi.org/10.1021/acsanm.1c00960.

https://oar.a-star.edu.sg/communities-collections/articles/17836

2574-0970

Institute for Infocomm Research