Failure analysis is crucial in improving semiconductor manufacturing yields. Yield improvement is done by collecting, analyzing, identifying the causes of defects, and applying corrective actions to resolve the root causes. With the ongoing miniaturization of TSVs, micro-bumps, RDLs, and other package interconnects , detecting defects in these buried interconnects is becoming more difficult as well as more important.
Traditionally semiconductor packages are cross-sectioned to identify internal process defects such as unsolders, solder shorts, and pad misalignment. Cross-sectioning is a destructive approach, is difficult to do, and provides information in a single 2D plane only. Due to the large effort and the destructive nature of this approach, the amount of data that can be generated is typically quite limited. The development of 3D x-ray microscopy provides industry with the capability to image and analyze buried features such as micro-bumps, TSVs, and other metallic structures using a non-destructive, 3-dimensional technology . At the same time, deep learning has revolutionized other technologies such as visual surveillance, predictive maintenance , object detection , and is now revolutionizing defect detection in semiconductors. When used together, the combination of 3D x-ray microscopy and deep learning is establishing a new paradigm in package inspection and metrology.
In this paper, we will present a novel method for automatically detecting internal anomalies in semiconductor packages and using deep learning to assess the attributes of these interconnects. Chips representative of stacked 2.5D packages were fabricated and assembled using thermo-compression bonding. Bonding parameters were varied in order to create packages with different bond line thickness, different solder fillet shapes, and various pad alignment scenarios. A commercial 3D x-ray imaging tool was used to create high-quality tomographies of these packages. Deep-learning and computer vision-based methods were employed to automatically detect internal features and measure attributes. A three-step procedure was used for data analysis. In the first step, a bounding box was detected for each region of interest (Copper Pillar, Pad, etc.) using a modified single shot detector object model. In the second step, we isolated features within the region of interest and performed 3D segmentation on them. The third and final step utilized automated 3D metrology using the segmented regions. Robust 3D computer vision techniques were deployed to measure the extent of voids which are key attributes for the chip fabrication and process control step. This is the first part of a multi-part paper.