Defect-Free Electroplating of High Aspect Ratio Through Silicon Vias: Role of Size and Aspect Ratio

Page view(s)
35
Checked on Jan 15, 2025
Defect-Free Electroplating of High Aspect Ratio Through Silicon Vias: Role of Size and Aspect Ratio
Title:
Defect-Free Electroplating of High Aspect Ratio Through Silicon Vias: Role of Size and Aspect Ratio
Journal Title:
2019 International Wafer Level Packaging Conference (IWLPC)
Publication Date:
28 November 2019
Citation:
C. A. Joshi et al., "Defect-Free Electroplating of High Aspect Ratio Through Silicon Vias: Role of Size and Aspect Ratio," 2019 International Wafer Level Packaging Conference (IWLPC), San Jose, CA, USA, 2019, pp. 1-6.
Abstract:
We study the role of via size and aspect ratio in defect-free electroplating of through silicon vias in 3DICs. Using a level-set curvature enhanced adsorbate coverage model, we simulate the electroplating of vias of various sizes and aspect ratio by varying the overpotential and the initial copper concentration. We find that as the via size and aspect ratio increases, the filling fraction reduces and voids are formed in the vias. Increasing overpotential also reduces the filling fraction. We show that in all these cases, increasing the initial copper concentration can result in increased filling of the vias of higher aspect ratios.
License type:
Funding Info:
A*STAR Defect Science Program Grant No. 1622400013
Description:
© 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
ISBN:
978-1-944543-12-9
978-1-7281-4583-9
Files uploaded:

File Size Format Action
iwlpc2019-joshi.pdf 328.22 KB PDF Open