Enabling Neuromorphic Computing: BEOL Integration of CMOS RRAM Chip and Programmable Performance

Enabling Neuromorphic Computing: BEOL Integration of CMOS RRAM Chip and Programmable Performance

IEEE International System-on-Chip Conference (SOCC 2019)

10.1109/SOCC46988.2019.1570553082

https://doi.org/10.1109/SOCC46988.2019.1570553082

Weijie Wang, Victor Yi-Qian Zhuo, Zhixian Chen, Hock Koon Lee, Minghua Li, Wendong Song

neuromorphic computing, RRAM, hardware accelerator

03 September 2019

W. Wang, V. Y. Zhuo, Z. Chen, H. K. Lee, M. Li and W. Song, "Enabling Neuromorphic Computing: BEOL Integration of CMOS RRAM Chip and Programmable Performance," 2019 32nd IEEE International System-on-Chip Conference (SOCC), Singapore, 2019, pp. 354-358, doi: 10.1109/SOCC46988.2019.1570553082.

Implementation of the neuromorphic computing requires a hardware network system to mimic the functionality of biological neural systems. The development of digital non-volatile resistive memory in a large and dense array is maturing and it provides a tremendous commercial opportunity to enable the hardware accelerator development. In this work, we have designed the RRAM device structures and developed the back-end-of-line (BEOL) CMOS integration processes to fabricate the memory chips of 64Kb array, and achieved a high fabrication yield > 99.79% with programmable characteristics to meet the requirements of different application algorisms. The chips as the building block of artificial neuromorphic network have low writing energy, fast writing speed, high endurance and retention. Most importantly, we demonstrated the remarkable capabilities chips to facilitate neuromorphic computing.

PublisherCopyrights

The manuscript is supported by the Agency for Science, Technology and Research (A*STAR) SERC grant A1687b0033.

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Institute of Microelectronics