FPGA design and implementation of the Joint Viterbi Detector Decoder

FPGA design and implementation of the Joint Viterbi Detector Decoder
Title:
FPGA design and implementation of the Joint Viterbi Detector Decoder
Other Titles:
2016 10th International Conference on Signal Processing and Communication Systems (ICSPCS)
Publication Date:
19 December 2016
Citation:
B. Hamadicharef and K. S. Chan, "FPGA design and implementation of the Joint Viterbi Detector Decoder," 2016 10th International Conference on Signal Processing and Communication Systems (ICSPCS), Gold Coast, QLD, 2016, pp. 1-5.
Abstract:
In this paper we present the design and implementation of the Joint Viterbi Detector Decoder (JVDD) algorithm onto a Field Programmable Gate Array (FPGA). Based on the reference C-code, we implemented each individual functions of the JVDD in VHSIC Hardware Description Language (VHDL) and tested against the results of the reference C-code. They include the calculation of the noise free metrics, of the branch metrics, the copy-and-extend of the survivors' bit-patterns, survivors' kill-by-ParityCheck, kill-by-Threshold and kill-by-Capping, as well as sorting. Some modules exploit the full hardware parallelism, while trying to automate the generation of VHDL modules together with their test-benches. Our JVDD implementation can be parameterized for any Parity Check Matrix (PCM) size and code rate (R), with the current focus for a CWL = 64 and R = 0.5, scaling up to larger CWLs using Block RAMs (BRAMs). Finally, a systematic study of the JVDD memory requirements for longer CWLs (e.g. 4096) identified the need for larger FPGA, such as Xilinx Virtex-7 UltraScale.
License type:
PublisherCopyrights
Funding Info:
National Research Fund (NRF) Singapore (The Joint Viterbi Detector/Decoder (JVDD) for Satellite Communications, NRF2013SAS-SRP001047)
Description:
ISBN:
978-1-5090-0941-1
978-1-5090-0940-4
978-1-5090-0942-8
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