A 0.034% Charge-Imbalanced Neural Stimulation Front-End (SFE) IC with On-Chip Voltage Compliance Monitoring Circuit and Analysis on Resting Potential by Utilizing the SFE IC

A 0.034% Charge-Imbalanced Neural Stimulation Front-End (SFE) IC with On-Chip Voltage Compliance Monitoring Circuit and Analysis on Resting Potential by Utilizing the SFE IC
Title:
A 0.034% Charge-Imbalanced Neural Stimulation Front-End (SFE) IC with On-Chip Voltage Compliance Monitoring Circuit and Analysis on Resting Potential by Utilizing the SFE IC
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IEEE Transactions on Circuits and Systems I: Regular Papers
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Publication Date:
01 October 2019
Citation:
Y. Jeon, L. Yao, Y. Gao and M. A. Arasu, "A 0.034% Charge-Imbalanced Neural Stimulation Front-End (SFE) IC With on-Chip Voltage Compliance Monitoring Circuit and Analysis on Resting Potential by Utilizing the SFE IC," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 10, pp. 3797-3810, Oct. 2019. doi: 10.1109/TCSI.2019.2919333
Abstract:
The proposed SFE IC adopts an eight-channel H-bridge structure with an integrated voltage compliance monitoring circuit. It has stimulation current ranged from 0.78mA to 6.2mA selected by 3b control and the stimulation current level can be controlled with 7b resolution within a selected current range. The current range can be expanded by using a high current option ranged from 2.71mA to 21.7mA under 3b control. The worst DNL and INL of the stimulation current source are 0.32 LSB and 0.3 LSB, respectively, from all the current ranges. The average mismatch between the cathodic and anodic current pulses in a biphasic stimulus is measured as 0.034% without using charge balancing techniques. The voltage compliance monitoring circuit is based on triode detection of a sensing MOSFET and it shows the detection accuracy of 45mV from its measurement results. The maximum steady-state voltage across the electrodes/ solution interface (resting potential) is also rigorously analyzed and verified through bench-top and saline experiments by utilizing the proposed stimulator. The SFE IC was fabricated in 0.18μm 24 V CMOS process.
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ISSN:
1549-8328
1558-0806
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