F. X. Che, M. Kawano, M. Z. Ding, Y. Han and S. Bhattacharya, "Study on Low Warpage and High Reliability for Large Package Using TSV-Free Interposer Technology Through SMART Codesign Modeling," in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 7, no. 11, pp. 1774-1785, Nov. 2017. doi: 10.1109/TCPMT.2017.2707567
Through-silicon via (TSV)-free interposer (TFI) technology eliminates TSV fabrication and reduces manufacturing and material cost. In this paper, structure– material–assembly–reliability–thermal (SMART) codesign modeling methodology is established for a package using TFI technology by considering wafer process, package assembly and package/board-level temperature cycling reliability, and thermal performance to optimize structure design, assembly process, and material selection. Experimental results are used to validate wafer warpage modeling results first. Through wafer-level modeling, suitable carrier and molding compound materials are recommended to control wafer warpage less than 2 mm for 12-in molded wafer. Effects of coefficient of thermal expansion of package substrate and stiffener on package warpage induced
by assembly reflow process are simulated and analyzed. The recommended materials and geometry design based on thermal cycling reliability simulation are aligned with that from wafer and package warpage simulation results. The final test vehicle design and material selection are determined based on SMART codesign modeling results for achieving successful TFI wafer process and package assembly and long-term board-level reliability.