Process and Reliability of Large Fan-Out Wafer Level Package based Package-on-Package

Process and Reliability of Large Fan-Out Wafer Level Package based Package-on-Package
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Process and Reliability of Large Fan-Out Wafer Level Package based Package-on-Package
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2017 IEEE 67th Electronic Components and Technology Conference (ECTC)
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30 May 2017
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This paper presents, the development of large multi-chip fan-out wafer level package (FOWLP) based Package-on-Package (PoP) using mold-First FOLWP integration flow for mobile applications. As part of this development, conventional mold-First FOWLP wafer reconstruction process has been optimized and selected key materials to overcome the challenges such as die shift, die protrusion, warpage. Fine pitch multi-layer RDL of LW/LS of 5μm/5μm fabrication, through mold via (TMV) formation, thin wafer handling for backside RDL and PoP assembly processes were also optimized. TMV process using laser drilling and sidewall plated Cu with polymer filling has been demonstrated. Using these optimized processes multi-chip FOWLP of 15 mm x 15 mm with double side RDL and high I/O count ~1360 I/Os at 400μm pitch was successfully demonstrated. Assembly process flow was optimized for PoP assembly on test boards, and build the PoP samples for reliability testing. FOWLP PoP samples were passed component level tests like MST L1, MST L3, HAST, MST L1+TC and board level tests 500 TCOB cycles and 30 drops of board level drop test. Failure analysis was carried out using CSAM, cross-sectioning and SEM. Reliability tests and failure analysis results will be presented.
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