The electrical interconnect technique of the advanced packaging process has been evolving. Generally, in order to provide increased functionality and performance in the same volume, the advanced packaging processes used multiple chips to integrate the systems into a single package. The development of these advanced packaging trends is being driven primarily by the rapid growth in mobile handheld devices such as smartphones. A lot of development and production are reached, inclusive of wafer level packaging, Cu pillar on through silicon via interposer, fan out wafer level packaged, and many more. The fine pitch copper pillar
process is subjected to be replaced by the controlled collapse chip connection bump in the new system package designs. The wafer level packaging fabrication used the spun process of photo resist to plating the copper pillar. However, when the thicknesses of photo resist had been increased to 100μm, there are many process and manufacturing challenges; the thickness of photo resist coating and the uniformity of photo resist, throughput and costs of materials. And emerging as an attractive alternative is the use of dry film resist materials. Dry film photoresist materials were used not only on fabricating the PCB but also on WLP fabrication process in recent years.
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