Development of Via-Last (VL) Through Silicon Via (TSV) has been pursued for its added benefits of process flow simplicity, cost and flexibility. A cost-effective, CMP-less VL TSV integration flow has been proposed for a further 9% cost reduction. This flow makes it also suitable for fine line RDL applications <2um. This paper reports and compares the electrical characterization of conventional and CMP-less VL TSV before thermal stressing. After time zero electrical testing, the VL TSV samples from both integration schemes is subjected to thermal stress condition of -40oC to 125oC for 250 cycles before repeating the same electrical characterization. TSV resistance and leakage current data before and after thermal stress shows
that there is little difference in terms of electrical performance between conventional and CMP-less VL TSVs.
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