Electrical Characterization of CMP-less Via-Last TSV under Reliability Stress Conditions

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Electrical Characterization of CMP-less Via-Last TSV under Reliability Stress Conditions
Title:
Electrical Characterization of CMP-less Via-Last TSV under Reliability Stress Conditions
Journal Title:
2017 IEEE 67th Electronic Components and Technology Conference (ECTC)
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Publication Date:
30 May 2017
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Abstract:
Development of Via-Last (VL) Through Silicon Via (TSV) has been pursued for its added benefits of process flow simplicity, cost and flexibility. A cost-effective, CMP-less VL TSV integration flow has been proposed for a further 9% cost reduction. This flow makes it also suitable for fine line RDL applications
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(c) 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works.
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